Hardware Reference · x86 · 1989–1999
486-class x86: architecture, silicon, and the clone wars
5-stage pipeline 8–16KB L1 socket 1/2/3 Pipeline, cache, MMU, clock multiplication, the electrical evolution across sockets, the seven-manufacturer clone landscape, and the OverDrive upgrade path, anchored to a real chip: the AMD Am486DE2-66V8TGC.
Core pipeline
Five stages, one clock for the common case: the 486 was the first x86 core to pipeline instruction execution the way later RISC designs would — fetch, decode1, decode2, execute, writeback run as overlapping stages rather than one instruction finishing before the next starts. Combined with the on-die L1 cache, this is why a 486 at a given clock ran roughly twice the throughput of a 386 at the same clock on integer code, despite a similar instruction set and few new opcodes.
Instructions arrive through a 32-byte prefetch queue holding roughly ten instructions ahead of execution. Register-to-register and simple ALU ops complete in one cycle once the pipeline is full; memory-referencing and multi-cycle instructions (multiply, string ops, far jumps) stall stages behind them, same as any classic pipeline hazard. There is no superscalar issue, that's the Pentium's contribution two generations later.
Cache and memory management
- Base parts shipped a unified 8KB L1, code and data sharing one 4-way set-associative array running at core clock, not bus clock. Enhanced-family parts (AMD's later Am486DX/DX4 revisions, Am5x86) doubled this to 16KB.
- Cache policy split the product line in two: write-through on early/base parts, write-back on Enhanced parts, selectable in some models via the WB/WT pin or a control bit. Write-back models use a MESI coherency scheme on the cache line state.
- There is no on-die L2. Motherboards carried external SRAM, commonly socketed as a COAST module, up to 256KB in practice. Skimping on L2 was a real-world differentiator: period benchmarks found a DX2 with a well-populated 128KB+ L2 landing within a few percent of a true 50MHz DX, while cache-starved boards lagged badly.
- The on-chip MMU handles both segmentation and paging: two-level page tables, 4KB pages, and a 32-entry 4-way TLB with pseudo-LRU replacement sitting in front of the page walk.
- Four operating modes: real mode (power-on default, 8086-compatible), protected mode, virtual-8086 mode (running real-mode code inside a protected-mode OS), and System Management Mode for power control, entered via a dedicated SMI# pin independent of the OS.
The FPU line: DX, SX, and the 487 fiction
DX parts carry a fully integrated x87 FPU on-die: eight 80-bit extended-precision registers, IEEE 754 single/double/extended formats, error signaling through the FERR and IGNNE pins. SX parts are the same die with the FPU disabled, sometimes because a defect landed there during test and the rest of the chip was still good, sometimes purely for market segmentation once yields improved.
The 487SX upgrade fiction: Intel sold the i487SX as a "math coprocessor" for SX systems that came with a spare upgrade socket. It was not a coprocessor. It was a complete 486DX with a different pin key, and installing one shut the original SX off the bus entirely via an UP# signal. From a software standpoint a 487SX-equipped system simply is a 486DX. This pattern, selling a full CPU as an "upgrade part" that disables the resident chip, became the template for the entire OverDrive line that followed.
Clock multiplication
| line | multiplier | typical range | note |
|---|---|---|---|
DX | 1x | 16–50MHz | core clock = bus clock, no CLKMUL pin logic active |
DX2 | 2x | 40–100MHz core | 8KB cache masks bus latency, up to 100% gain for zero board changes |
DX4 | 3x | 75–120MHz core | the name lies — it is a tripler, not a quadrupler |
Am5x86 | 4x | 133–200MHz core | AMD-only, 33MHz bus × 4, marketed as P75 despite being a 4th-gen core |
The multiplier is a PLL fed by an external CLKMUL selection, generating an internal clock some ratio of the bus clock without touching bus timing or peripheral compatibility. This is the single fact that made the entire OverDrive retail upgrade market possible: a socket swap could double or triple compute throughput on a board that never changed.
Socket and electrical evolution
| socket | pins | voltage | notable |
|---|---|---|---|
| Socket 1 | 168, LIF | 5V only | original 486 socket, no ZIF, extraction tool required |
| Socket 2 | 238, ZIF | 5V | added the OverDrive upgrade socket spec |
| Socket 3 | 237, ZIF | 5V and 3.3V | the flexible one — DX4, Am5x86, and this DE2-66 all drop in |
Voltage is not optional to get right. Early/base parts want 5V; from the DX4 generation onward, 3.3V core with 5V-tolerant I/O became standard, cutting power roughly in half at a given clock. A Socket 3 board's voltage jumper or onboard VRM has to match the chip before power-on, mismatches destroy 3.3V-only silicon fast.
AMD's die and package chronology
AMD shipped four distinct Am486 dies over the product's life, each with several package revisions. This is the level of detail that actually identifies what's in your hand, since the visible part number alone (V8T, V16B, etc.) only tells you voltage, cache size, and write policy, not silicon generation.
- 700nm / 8KB, ~90mm², write-through only. First package 24361 (Mar 1993–Nov 1994, steppings B/C/D/E, 5V), then 25220 as the 3.3V transition package.
- 500nm / 8KB, ~52mm², adds write-back support in later revisions. Package 25253 was the workhorse (DX2-66 through DX4-100/120); 25498 is the last-generation package, briefly used for DX4-100 and then kept in production for years specifically for the embedded Am486DE2-66V8TGC.
- 500nm / 16KB, the rarest die. Poor yield on the full 16KB config meant most surviving chips shipped with half the cache fused off.
- 350nm / 16KB, package 25544. Write-back standard, PLL supports 2x/3x/4x depending on binning. This is the Am5x86 die.
The clone manufacturer landscape
OverDrive: the upgrade-socket economy
Two physical formats: ODP parts carried an extra 169th key pin and an UP# signal, meant for the spare socket next to a soldered-down SX. ODPR parts used the standard 168-pin interface and required pulling the existing CPU first, Intel shipped an extraction tool in the box for exactly this. Early naming was actively confusing: the entry ODP486SX-25 was internally a DX2-50, named for what it replaced rather than what it was, a scheme Intel abandoned by 1994 in favor of straightforward frequency labels like DX2ODPR66.
DX4 OverDrive added a real complication: standard DX4 silicon ran 3.3V-class (3.45V nominal), incompatible with older 5V-only boards. The DX4 OverDrive solved this with an onboard voltage regulator and a noticeably taller heatsink, letting a 5V-only Socket 1/2 board take a tripled-clock part it electrically couldn't otherwise run. Pentium OverDrive pushed this furthest: a genuine Pentium core, bus-narrowed from 64-bit to the 486's 32-bit interface and given double L1 to compensate, at 63MHz (Feb 1995) and later 83MHz, with its own onboard VRM and a heatsink fan powered straight from the CPU socket.
The DX/50 cautionary tale
Intel's 486DX-50 (1991) is the case study in why clock-doubling won over raising the bus clock directly. Running the external bus at a genuine 50MHz, rather than 25 or 33MHz multiplied up, meant every peripheral on the board, cache SRAM, chipset, the works, had to be rated for 50MHz too. 20ns cache SRAM was roughly 24× the price of contemporary DRAM per byte. The 50MHz emissions profile also pushed systems out of the FCC's Class B (residential) certification and into Class A (business-only), making it a de facto server part by regulation as much as by price.
Intel had to halt shipments in August 1991 after early units overheated badly enough to shut systems down, the first 486 that genuinely needed a heatsink. It stayed in production into late 1993, and period benchmarks show it holding its own against the DX2/66 that superseded it, sometimes winning on memory-bound workloads, but by the 1993 buyer's guides only 4 of 89 tested system lines still offered it against 83 offering the DX2/66. The market had already decided the multiplier trick was the better engineering answer.
This chip: Am486DE2-66V8TGC
| field | value |
|---|---|
| decode | DE2 embedded clock-doubled · 66 66MHz core / 33MHz bus · V 3.3V · 8 8KB cache · T write-through |
| functional identity | electrically and functionally a standard Am486DX2-66 — embedded Am486 parts were not cut down from their desktop SX/DX counterparts |
| package | 25498, the last-generation Am486 package, in production for this specific part into 1999 |
| socket | 168-pin CPGA, drops into Socket 3 |
| TDP | ~2.4W typical for the 66MHz/3.3V configuration |
The lifecycle is the interesting part: this exact package/part combination stayed in AMD's catalog years after the desktop DX2-66 had been obsoleted twice over by the DX4 and Am5x86 lines, purely because embedded and industrial customers needed a long, stable production run rather than the fastest available part. A date code reading week 21 of 1998 on a chip like this is exactly consistent with that extended tail.
Where this still matters
- Deterministic timing and a fully public, non-microcode-patched instruction set make the 486 a clean platform for teaching pipelining, cache hierarchy, and real-to-protected mode transitions with hardware you can actually put a scope on.
- Embedded and industrial modules (PC/104 and similar form factors) kept 486-class cores in production well past 2000 for the same reason this DE2 part existed: certified, unchanging behavior matters more than speed in a controller that can't be casually revalidated.
- Cycle-accurate emulation (PCem) and FPGA cores (MiSTer) now cover most of the same architecture faithfully enough for software archaeology, without the capacitor-aging and PSU risk of forty-year-old boards, real silicon still wins for hardware-level debugging and genuine BIOS/IRQ behavior.